CAMs can include conventional semiconductor memory (e.g., static random access memory (SRAM)) and comparison circuitry that enables a search operation to be completed rapidly (e.g., in a single clock cycle). This ability allows hardware implementation of search algorithms, which provide greater speed than software implemented searches. In a physical design of a CAM array structure, it is desirable to have a regular shape, such as a rectangle, in order to reduce the size of the CAM array structure and make efficient use of space. Speed and power consumption are issues in high performance designs that are addressed by avoiding unnecessary parasitic capacitance. A physical layout that reduces critical area and routing reduces parasitic capacitance. However, certain aspects of CAM designs make achieving maximum efficiency in their physical design challenging.
FIG. 1 is a conceptual top level cache block diagram 100 of CAM 110 and RAM 130 arrays having rows <0>, <1>, . . . <n>. The CAM 110 and RAM 130 are separated by control circuit 120. As shown in FIG. 1, the CAM array 110 and the RAM array 130 each have the same number of rows. To produce an efficient design, it is desirable to match the CAM array 110 row height to the RAM array 130 row height, as shown in FIG. 1, so that the overall shape of the CAM array has a rectangular shape, when viewed in the x and y plane (i.e., the footprint of the RAM array), thereby making efficient use of the area used. For purposes of this disclosure, the “row height” refers to the distance in the y-direction, as shown, for example, in FIG. 1.
In a static random access memory (SRAM) design, a 6-T storage cell often defines the minimum possible row height of the array structure. This RAM cell is given special ground rule waivers from a foundry so that process technologies can be pushed to the limit to produce a minimum area cell. FIG. 2A is a schematic of a conventional RAM array cell 200 which is composed of a 6-T storage cell. FIG. 2B shows a RAM array cell layout. Generally, the RAM cell 201 is provided by the foundry. Significant design effort is applied to reduce the physical size of the RAM cell and thereby make efficient use of the area used per cell, as shown in FIGS. 1 and 2B. Further, when designing the CAM array 110, the area on the CAM side (i.e., CAM array 110 in FIG. 1) should also be reduced because it is desirable to obtain a one-to-one correspondence between the height of the CAM array 110 side and the RAM array 130 side.
With reference again to FIG. 1, a content addressable memory (CAM) array 110 typically includes a storage cell, such as the 6-T RAM cell 201, and compare circuitry for each bit in the array. To produce an efficient design, it is desirable to at least substantially match the CAM array 110 row height to the RAM array 130 row height such that there is generally a one-to-one correspondence of the CAM array 110 and the RAM array 130.
For example, one way to match the CAM array 110 row height to the RAM array 130 row height is to limit the height of the CAM cells to the height of the RAM cell 201 which is included therein. Accordingly, there is a one-to-one correspondence in height between the height of each row of the CAM array 110 and each row of the RAM array 130, as shown in FIG. 1.
FIG. 3 shows one conventional way of implementing a matched row height cache design. Particularly, FIG. 3 shows a non-interleaved set CAM array cell layout 300 in which the height of the compare stacks 310 and 320 matches the height of the storage cell (i.e., RAM array cell 301). In the conventional designs, to maintain the common height, the nodes 315 and 316, which can be coupled to a matchline, are split up on either side of the cell, which results in additional capacitance.
In FIG. 3, the storage cell, i.e., RAM array cell 301, is laid out such that two compare stacks 310 (false/compliment) and 320 (true), are on each side of the RAM array cell 301. The row height of each of the compare stacks 310 and 320 is designed to be no larger than the row height of the RAM array cell 301. The nodes 315 and 316 can be connected by a net. For purposes of this disclosure, a net is a wire connecting two or more nodes (two or more points). When rows are stacked sequentially, as in FIG. 3, and compare lines are vertically aligned, significant capacitance is added to the nodes 315, 316. The matchline nets are connected across each bit within a row, but may be unique from row to row, as illustrated in FIG. 4.
FIG. 4 is an illustration of a conventional CAM design 400 in which rows within an array are placed consecutively. Each CAM array cell is identified by dashed lines. In FIG. 4, the compare lines are vertically aligned. However, in FIG. 4, the compare transistor stacks each have their own matchline, which results in increased capacitance. That is, in FIG. 4, the matchlines do not share diffusion.
As described above, the conventional CAM array designs, for example, as shown in FIGS. 3 and 4, result in increased capacitance which degrades the performance of the memory array. Thus, there is a need for a CAM array design that makes efficient use of space, reduces critical area and routing, and reduces parasitic capacitance.